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Computer Patents


Lumped together within the broad term "computer patents" are numerous technological areas. The technology of semiconductors and the patent drafting work done on semiconductor patents, for example, is very different than the technology and patent work done on hard drive read/write systems, which is very different in turn from what is necessary to understand and describe a Fiber Channel Arbitrated Loop architecture, a RAID system or an I/O fail-over queue. We've worked in all of these technologies and more at Barber Legal.

Are Hardware Patents Much Different From Software Patents?

Yes, very. Looking over the patent excerpts below and comparing them to the excerpted patents on our page about software patents, readers will see that whereas hardware patents often involve semiconductor physics or electronic or mechanical engineering, software patents are more likely to involve logic and data structures. So while the overlap is large, it is not as large as might be expected.

Examples of Hardware Patents Past

We've included as examples abstracts taken from patents previously granted. Some of these patents were close to history, some are unknown, a few were chosen whimsically. Note that these are not chosen for being patents done by Barber Legal, we're not advertising here, nor promising that "we can get you a patent like this", what we are doing is giving you an idea of the sorts of things that have been done in the past by inventors and patent attorneys around the world.


United States Patent 6,069,764
Morris , et al.
May 30, 2000

Compensation for repeatable run-out error

Abstract:
A method and apparatus for compensating for repeatable run-out errors in a disc drive is disclosed. The compensation is created by determining transfer function values for a servo loop in the drive as well as a sequence of repeatable run-out values for a portion of a disc. The repeatable run-out values are divided by respective transfer function values to produce compensation values that are inverse transformed to produce time-domain compensation values. These time-domain compensation values are injected into the servo loop to compensate for repeatable run-out errors.

Inventors: Morris; John Christopher (Minneapolis, MN); Pollock; Brian Robert (Eden Prairie, MN); Ellis; Timothy Francis (Tonka Bay, MN)
Assignee: Seagate Technology, Inc. (Scotts Valley, CA)
Appl. No.: 106443
Filed: June 29, 1998

Primary Examiner: Burgess; Glenton B.
Assistant Examiner: Habermehl; James L
Attorney, Agent or Firm: Westman, Champlin & Kelly, PA


United States Patent 6,130,841
Tanaka , et al.
October 10, 2000

Semiconductor nonvolatile memory apparatus and computer system using the same

Abstract:
After decreasing the threshold voltages of a plurality of memory cells collectively or selectively, the presence or absence of any memory cell of which the threshold voltage has dropped below a predetermined voltage verified collectively for each of memory cell groups connected to word line (low-threshold value verification), and any memory cell of which the threshold voltage has excessively dropped is selectively written. Also, the well of each of memory cell is formed in the region of an element isolation layer for isolating it from the substrate of a memory apparatus, and a negative voltage is supplied to the memory well distributively with a positive voltage applied as a word line voltage, thus supplying them as erase operation voltages. The absolute value of the memory well voltage is set substantially equal to or lower than the word line voltage for the read operation. Sectors constituting each memory mat includes a sector (selected sector) selected for the erase operation with each word line thereof supplied with a positive voltage, a sector (non-selected sector) not selected for the erase operation with a word line voltage different from a memory well voltage, and further a sector (completely non-selected sector) not selected for the erase operation with a word line voltage equal to the voltage between a source and a drain of the memory cell.

Inventors: Tanaka; Toshihiro (Akiruno, JP); Kato; Masataka (Koganei, JP); Tsuchiya; Osamu (Hamura, JP); Nishimoto; Toshiaki (Tachikawa, JP)
Assignee: Hitachi, Ltd. (Tokyo, JP)
Appl. No.: 432070
Filed: November 2, 1999

Foreign Application Priority Data
Aug 31, 1995[JP] 7-223016
Sep 01, 1995[JP] 7-224991
Sep 08, 1995[JP] 7-231025

Primary Examiner: Phan; Trong
Attorney, Agent or Firm: Antonelli, Terry, Stout & Kraus, LLP


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